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		<title>imported&gt;Atariki recovery: Reconstructed from archived HTML; see provenance manifest</title>
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		<summary type="html">&lt;p&gt;Reconstructed from archived HTML; see provenance manifest&lt;/p&gt;
&lt;p&gt;&lt;b&gt;Nowa strona&lt;/b&gt;&lt;/p&gt;&lt;div&gt;&amp;lt;pre&amp;gt;Register summary for selected Western Digital floppy drive controllers&lt;br /&gt;
&lt;br /&gt;
Unified format&lt;br /&gt;
Greg Cook, 19/Aug/2005&lt;br /&gt;
&lt;br /&gt;
Command register&lt;br /&gt;
&lt;br /&gt;
Model&lt;br /&gt;
WD2795/WD2797            x   x   x   x   . . . x    x   . . x   . x&lt;br /&gt;
WD2791/WD2793            x   x   x   x   . . x .    x   . x .   . x&lt;br /&gt;
WD1773                   x   x   x   x   . x . .    x   . x .   . x&lt;br /&gt;
WD1770/WD1772            x   x   x   x   x . . .    x   x . .   x .&lt;br /&gt;
&lt;br /&gt;
Type    Command         b7  b6  b5  b4     b3      b2    b1     b0&lt;br /&gt;
   I    Restore          0   0   0   0   H X h h    V   r r r   r r&lt;br /&gt;
   I    Seek             0   0   0   1   H X h h    V   r r r   r r&lt;br /&gt;
   I    Step             0   0   1   u   H X h h    V   r r r   r r&lt;br /&gt;
   I    Step in          0   1   0   u   H X h h    V   r r r   r r&lt;br /&gt;
   I    Step out         0   1   1   u   H X h h    V   r r r   r r&lt;br /&gt;
  II    Read sector      1   0   0   m   H S S L    E   0 C U   0 0&lt;br /&gt;
  II    Write sector     1   0   1   m   H S S L    E   P C U   a a&lt;br /&gt;
 III    Read address     1   1   0   0   H 0 0 0    E   0 0 U   0 0&lt;br /&gt;
 III    Read track       1   1   1   0   H 0 0 0    E   0 0 U   0 0&lt;br /&gt;
 III    Write track      1   1   1   1   H 0 0 0    E   P 0 U   0 0&lt;br /&gt;
  IV    Force interrupt  1   1   0   1   I I I I    I   X I I   X I&lt;br /&gt;
&lt;br /&gt;
Parameters:&lt;br /&gt;
        0 = always 0&lt;br /&gt;
        1 = always 1&lt;br /&gt;
        X = not used (reset to 0)&lt;br /&gt;
&lt;br /&gt;
        a = Data address mark&lt;br /&gt;
                0 = Data address mark&lt;br /&gt;
                1 = Deleted-data address mark&lt;br /&gt;
        C = Side compare&lt;br /&gt;
                0 = Disable side compare&lt;br /&gt;
                1 = Enable side compare&lt;br /&gt;
        E = Settling delay&lt;br /&gt;
                0 = No delay&lt;br /&gt;
                1 = Delay: 15 ms for WD279x at 2 MHz, and WD1772&lt;br /&gt;
                           30 ms for WD279x at 1 MHz, and WD1770/WD1773&lt;br /&gt;
        h = Head load&lt;br /&gt;
                0 = Unload head at beginning&lt;br /&gt;
                1 = Load head at beginning&lt;br /&gt;
        H = Motor On&lt;br /&gt;
                0 = Enable spin-up sequence&lt;br /&gt;
                1 = Disable spin-up sequence&lt;br /&gt;
        I = Interrupt&lt;br /&gt;
                I0 = Interrupt on not ready to ready transition&lt;br /&gt;
                I1 = Interrupt on ready to not ready transition&lt;br /&gt;
                I2 = Interrupt on index pulse&lt;br /&gt;
                I3 = Interrupt immediately&lt;br /&gt;
                        0 = No interrupt&lt;br /&gt;
                        1 = Raise interrupt on this condition&lt;br /&gt;
                I0..I3&lt;br /&gt;
                        all 0 = terminate current command without interrupt&lt;br /&gt;
&lt;br /&gt;
        L = Interpretation of ID field&lt;br /&gt;
                The sector length in bytes is determined from the following&lt;br /&gt;
                table:&lt;br /&gt;
                   LSBs of sector length in ID field&lt;br /&gt;
                          00      01      10      11&lt;br /&gt;
                L&lt;br /&gt;
                0        256     512    1024     128&lt;br /&gt;
                1        128     256     512    1024&lt;br /&gt;
                WD177x and WD2791/3 operate with L = 1.&lt;br /&gt;
        m = Multiple sectors&lt;br /&gt;
                0 = Single sector&lt;br /&gt;
                1 = Multiple sectors&lt;br /&gt;
        P = Write precompensation&lt;br /&gt;
                0 = Enable write precompensation&lt;br /&gt;
                1 = Disable write precompensation&lt;br /&gt;
        r = Stepping rate&lt;br /&gt;
                            Model, clock frequency&lt;br /&gt;
                         WD1770  WD1772  WD279x  WD279x&lt;br /&gt;
                        /WD1773          @2 MHz  @1 MHz&lt;br /&gt;
                r1  r0&lt;br /&gt;
                 0   0     6 ms    6 ms    3 ms    6 ms&lt;br /&gt;
                 0   1    12 ms   12 ms    6 ms   12 ms&lt;br /&gt;
                 1   0    20 ms    2 ms   10 ms   20 ms&lt;br /&gt;
                 1   1    30 ms    3 ms   15 ms   30 ms&lt;br /&gt;
        S = Side comparand&lt;br /&gt;
                0 = Compare for side 0&lt;br /&gt;
                1 = Compare for side 1&lt;br /&gt;
        u = Update track (T in 279x datasheet)&lt;br /&gt;
                0 = No update&lt;br /&gt;
                1 = Update track register&lt;br /&gt;
        U = Update SSO (Side select)&lt;br /&gt;
                0 = Update SSO to 0&lt;br /&gt;
                1 = Update SSO to 1&lt;br /&gt;
        V = Verify on track&lt;br /&gt;
                0 = No verify&lt;br /&gt;
                1 = Verify on destination track&lt;br /&gt;
&lt;br /&gt;
Status register&lt;br /&gt;
&lt;br /&gt;
Model&lt;br /&gt;
WD2795/WD2797           . x   . x   . . x   . x   . x   x   x   x&lt;br /&gt;
WD2791/WD2793           . x   . x   . . x   . x   . x   x   x   x&lt;br /&gt;
WD1773                  . x   . x   . x .   . x   . x   x   x   x&lt;br /&gt;
WD1770/WD1772           x .   x .   x . .   x .   x .   x   x   x&lt;br /&gt;
&lt;br /&gt;
Type    Command         b7    b6     b5     b4    b3   b2  b1  b0&lt;br /&gt;
   I    (all type Is)   M n   X w   s h h   R R   c c   T   I   b&lt;br /&gt;
  II    Read sector     M n   X 0   a a a   R R   c c   d   q   b&lt;br /&gt;
  II    Write sector    M n   w w   a f 0   R R   c c   d   q   b&lt;br /&gt;
 III    Read address    M n   X 0   a 0 0   R R   c c   d   q   b&lt;br /&gt;
 III    Read track      M n   X 0   a 0 0   R 0   c 0   d   q   b&lt;br /&gt;
 III    Write track     M n   w w   a f 0   R 0   c 0   d   q   b&lt;br /&gt;
  IV    Force interrupt&lt;br /&gt;
        -while busy     - -   - -   - - -   - -   - -   -   -   0&lt;br /&gt;
        -while idle     M n   X w   s h h   R R   c c   T   I   0&lt;br /&gt;
   -    Idle            M n   X w   s h h   R R   c c   T   I   b&lt;br /&gt;
&lt;br /&gt;
Parameters:&lt;br /&gt;
        0 = always 0&lt;br /&gt;
        X = not defined&lt;br /&gt;
        - = retains previous value&lt;br /&gt;
&lt;br /&gt;
        a = Data address mark&lt;br /&gt;
                0 = Data address mark&lt;br /&gt;
                1 = Deleted-data address mark&lt;br /&gt;
        b = Busy&lt;br /&gt;
                0 = controller idle&lt;br /&gt;
                1 = controller busy&lt;br /&gt;
        c = CRC error&lt;br /&gt;
                0 = CRC verified&lt;br /&gt;
                1 = CRC error&lt;br /&gt;
        d = Lost data (late register service)&lt;br /&gt;
                0 = no data lost&lt;br /&gt;
                1 = data lost&lt;br /&gt;
        f = Write fault&lt;br /&gt;
                0 = no write fault&lt;br /&gt;
                1 = write fault&lt;br /&gt;
        h = Head loaded&lt;br /&gt;
                0 = drive head not loaded&lt;br /&gt;
                1 = drive head loaded&lt;br /&gt;
        I = Index pulse&lt;br /&gt;
                0 = disc not at index mark (/IP = high)&lt;br /&gt;
                1 = disc at index mark (/IP = low)&lt;br /&gt;
        M = Motor on&lt;br /&gt;
                0 = drive motor off&lt;br /&gt;
                1 = drive motor on&lt;br /&gt;
        n = Not ready&lt;br /&gt;
                0 = drive ready&lt;br /&gt;
                1 = drive not ready&lt;br /&gt;
        q = Data request&lt;br /&gt;
                0 = Data register does not require service&lt;br /&gt;
                1 = Data register requires service&lt;br /&gt;
        R = Record not found&lt;br /&gt;
                0 = record found / verified on track&lt;br /&gt;
                1 = record not found / seek error&lt;br /&gt;
        s = Motor spin up sequence completed&lt;br /&gt;
                0 = spin up not completed&lt;br /&gt;
                1 = spin up completed&lt;br /&gt;
        T = Track 0&lt;br /&gt;
                0 = drive head not at track 0 (/TR00 = high)&lt;br /&gt;
                1 = drive head at track 0 (/TR00 = low)&lt;br /&gt;
        w = Write protect&lt;br /&gt;
                0 = disc write enabled&lt;br /&gt;
                1 = disc write protected&lt;br /&gt;
&lt;br /&gt;
Notes:&lt;br /&gt;
&lt;br /&gt;
The WD2791 and WD2795 have inverted data bus lines.&lt;br /&gt;
As noted elsewhere, the Busy flag may be left set when the FDC is idle, if&lt;br /&gt;
the FDC has been reset while a command was in progress.&lt;br /&gt;
If the WD1773 or WD279x is idle, and n = 1, flags c,h,I,R,T and w may be&lt;br /&gt;
invalid and contain 0.&lt;br /&gt;
The WD1770/2 status register description is taken from the datasheet; some&lt;br /&gt;
flags may have fixed values for certain commands, as with the other models.&lt;br /&gt;
&lt;br /&gt;
References:&lt;br /&gt;
&lt;br /&gt;
1770/2/3 Datasheet&lt;br /&gt;
        http://www.funet.fi/pub/cbm/documents/chipdata/wd177x/index.html&lt;br /&gt;
177x datasheet extracts and BBC disc hardware summary&lt;br /&gt;
        http://www.nvg.org/bbc/doc/wd1770.txt&lt;br /&gt;
        http://www.poppyfields.net/acorn/tech/1770.shtml&lt;br /&gt;
279x datasheet and application notes&lt;br /&gt;
        http://tcg.speccy.cz/zoom/files/wd2797.pdf&lt;br /&gt;
BBC Datasheets&lt;br /&gt;
        http://members.aon.at/~musher/bbc/datasheets.htm&lt;br /&gt;
&lt;br /&gt;
Disclaimer:&lt;br /&gt;
&lt;br /&gt;
The documentation in this file is for information only.  For a more&lt;br /&gt;
authoritative specification, refer to the manufacturer&amp;#039;s original&lt;br /&gt;
datasheets.  The author does not guarantee the suitability of the hardware&lt;br /&gt;
for use in any particular application, especially life support and/or&lt;br /&gt;
critical systems; for authoritative information on suitability refer to the&lt;br /&gt;
manufacturer.  Whilst every effort has been made to maintain accuracy,&lt;br /&gt;
this file may contain errors, inaccuracies or omissions which may or&lt;br /&gt;
may not also be present in the datasheet(s).  Specifications are subject to&lt;br /&gt;
change without notice.  This documentation is supplied without warranty,&lt;br /&gt;
not even the implied warranties of merchantability or fitness for a&lt;br /&gt;
particular purpose. In no event shall the author or his suppliers be liable&lt;br /&gt;
for any loss, damage, injury or death, of any nature and howsoever caused,&lt;br /&gt;
arising from the use of, or failure, inability or unwillingness to use,&lt;br /&gt;
this documentation.&lt;br /&gt;
&lt;br /&gt;
Greg Cook, [email address]&lt;br /&gt;
&amp;lt;/pre&amp;gt;&lt;br /&gt;
&lt;/div&gt;</summary>
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